In many electronics applications, an analog input signal is converted to a digital output signal (e.g., for further digital signal processing). For instance, in precision measurement systems, electronics are provided with one or more sensors to make measurements, and these sensors may generate an analog signal. The analog signal would then be provided to an analog-to-digital converter (ADC) as input to generate a digital output signal for further processing. In another instance, an antenna generates an analog signal based on the electromagnetic waves carrying information/signals in the air. The analog signal generated by the antenna is then provided as input to an ADC to generate a digital output signal for further processing.
ADCs can be found in many places such as broadband communication systems, audio systems, receiver systems, etc. ADCs can translate analog electrical signals representing real-world phenomenon, e.g., light, sound, temperature or pressure for data processing purposes. Designing an ADC is a non-trivial task because each application may have different needs in performance, power, cost and size. ADCs are used in a broad range of applications including communications, energy, healthcare, instrumentation and measurement, motor and power control, industrial automation and aerospace/defense. As the applications needing ADCs grow, the need for accurate and reliable conversion performance also grows.
Generally speaking ADCs are electronic devices that convert a continuous physical quantity carried by an analog signal to a digital number that represents the quantity's amplitude (or to a digital signal carrying that digital number). An ADC is typically composed of many devices making up an integrated circuit or a chip. An ADC can be defined by any one or more of the following application requirements: its bandwidth (the range of frequencies of analog signals it can properly convert to a digital signal), its resolution (the number of discrete levels the maximum analog signal can be divided into and represented in the digital signal), its linearity (e.g., how well the output data is proportionate to the input signal), and its signal to noise ratio (how accurately the ADC can measure signal relative to the noise the ADC introduces). Analog-to-digital converters (ADCs) have many different designs, which can be chosen based on the application requirements.
Overview
A successive-approximation-register analog-to-digital converter (SAR ADC) typically includes circuitry for implementing bit trials that converts an analog input to a digital output bit by bit. The circuitry for bit trials are usually weighted (e.g., binary weighted), and these bit weights are not always ideal. Calibration algorithms can calibrate or correct for non-ideal bit weights and usually prefer these bit weights to be signal-independent so that the bit weights can be measured and calibrated/corrected easily.
Usually, the SAR ADC measures an input against a reference during each bit trial, which can be embodied in the form of a reference charge being pulled from the reference. For SAR ADC performing a series of bit trials or decisions, the reference charge can be pulled from the reference during each bit decision, often at a particular rate of the ADC. To accommodate faster rates of ADCs, the charge is usually provided by adding an external low equivalent series resistance (ESR) capacitor between the reference and the ADC. The low ESR capacitor acts as an external charge “reservoir” which can support the instantaneous requirements of the ADC. The reference then serves the function of recharging this external reservoir capacitor. The charge being used during bit decisions are typically provided from the external reservoir capacitor to the ADC over bond wires, which can impede the speed of each bit decision, and thus the overall speed of the SAR ADC.
Embodiments disclosed herein relate to a unique circuit design of an SAR ADC, where each bit capacitor or pair of bit capacitors (in a differential design) corresponding to a particular bit trial or a particular bit weight has a corresponding dedicated on-chip reference capacitor. The speed of the resulting ADC is fast due to the on-chip reference capacitors (offering fast reference settling times), while errors associated with non-ideal bit weights of the SAR ADC are signal-independent (can be easily measured and corrected/calibrated). The present disclosure describes such important differences from other implementations and corresponding technical effects in detail.
Besides the circuit architecture, the present disclosure also describes a calibration scheme for calibrating such a SAR ADC. When reservoir capacitors are moved on-chip for individual bit decisions, a successive-approximation-register analog-to-digital converter (SAR ADC) has an addition source of error which can significantly affect the performance of the SAR ADC. Calibration techniques can be applied to measure and correct for such error in an SAR ADC using decide-and-set switching. Specifically, a calibration technique can expose the effective bit weight of each bit under test using a plurality of special input voltages and storing a calibration word for each bit under test to correct for the error. Such a calibration technique can lessen the need to store a calibration word for each possible output word to correct the additional source of error. Furthermore, another calibration technique can expose the effective bit weight of each bit under test without having to generate the plurality of special input voltages.